1. Field of the Invention
The present invention pertains generally to the field of radio frequency (RF) power transistor devices and, more specifically, to systems and methods that utilize the lid of a power transistor package to locate electrical circuit elements.
2. Background
The use of power transistor amplifiers in wireless communication applications is well known. With the considerable recent growth in the demand for wireless services, such as personal communication services (PCS), the operating frequency of wireless networks has expanded well into the gigahertz (GHz) frequencies. At these high frequencies, LDMOS transistors have been preferred for RF power amplification devices, e.g., in antenna base stations.
In a known system, an LDMOS RF power transistor package generally comprises a plurality of electrodes formed on a semiconductor die, each electrode comprising a number of transistors. The individual transistors of each electrode are connected to respective common input (gate) and output (drain) terminals formed on the surface of the die. A common ground (source) terminal substrate is formed on the underlying side of the die. The die is attached, e.g., by a known eutectic die attach process, to a metal flange serving as both a ground current reference and a heat sink. A thermally conductive, but electrically insulating, e.g., alumina, window is attached to the flange, surrounding the die. Respective input and output lead frames are attached, e.g., at opposing ends, to a top surface of the window, electrically isolated from the flange. The input and output lead frames are coupled to the respective electrode input and output terminals on the die by multiple wires, which are bonded to the respective terminals and lead frames.
By way of illustration, FIG. 1 shows a simplified electrical schematic of an unmatched LDMOS device, having an input (gate) lead 12, an output (drain) lead 14 and a source 16 through an underlying substrate. Transmission inductance through the input path, e.g., a plurality of bond wires connecting the input lead 12 to the common input terminal of the respective transistor fingers, is represented by inductance 18. Output inductance through the output path, e.g., a plurality of bond wires connecting the common output terminal of the respective transistors to the output lead 14, is represented by inductance 20.
FIG. 2 shows a known (matched) LDMOS power transistor device 40. The device 40 includes an input (gate) lead 42, output (drain) lead 44 and metallic (source) substrate 47 attached to a mounting flange 45. A first plurality of wires 48 couple the input lead 42 to a first terminal of an input matching capacitor 46. A second terminal of the input matching capacitor 46 is connected to ground (i.e., flange 45). A second plurality of wires 52 couple the first terminal of matching capacitor 46 to the respective input terminals 49 of a plurality of interdigitated electrodes 51 formed on a semiconductor die 50 attached to the metallic (source) substrate 47. By proper selection of the matching capacitor 46 and the series inductance of wires 48 and 52, the input impedance between the input lead 42 and electrode input terminals 49 can be effectively matched.
Respective output terminals 53 of the electrodes 51 are coupled to the output lead 44 by a third plurality of wires 54. In order to impedance match the output of the device, a shunt inductance is used. Towards this end, the output lead 44 is coupled to a first terminal of a DC blocking capacitor 58 (i.e., an AC short) by a fourth plurality of wires 60, the blocking capacitor 58 having a substantially lower value of reactance than the wires 60. A dielectric window substrate 24, e.g., made of aluminum oxide (xe2x80x9caluminaxe2x80x9d), is attached to the top surface of the mounting flange 45. The window substrate 24 has an inner perimeter 28, which defines a window 30 exposing a portion of the mounting flange surface 45.
Some known impedance matching techniques cannot be used in a conventional power transistor package because their elements occupy too much of the available substrate area. The circuit components needed to provide effective impedance matching will not physically fit in the available area on the mounting flange defined by the window substrate 24 or on the semiconductor die 50. Also, impedance matching networks that contain inductors or capacitors require an insulating substrate layer be added to the flange, or that the matching network be placed on a surrounding printed circuit board, outside the boundaries of the power transistor package. Further, some impedance matching techniques cannot be realized on the circuit board because the distance between the die and the outside of the package is too great.
It would therefore be desirable to provide an RF power transistor package that conserves space on the substrate as well as the surrounding circuit board, one in which complex impedance matching circuitry can be realized without requiring an insulating substrate layer.
A packaged integrated circuit constructed in accordance with the present invention solves the foregoing problems by incorporating circuit components in a lid that is adapted to engage with circuit components on a substrate.
In a preferred embodiment, the packaged integrated circuit includes a substrate that includes a first circuit component mounted thereon, a first conductor extending from the first circuit component, and a dielectric lid. The dielectric lid includes a component mounting surface, a second circuit component mounted on the component mounting surface, and a second conductor extending from the second circuit component. The dielectric lid is adapted to engage with the substrate such that the first circuit component is in electrical communication with the second circuit component.
In accordance with another aspect of the present invention, an RF power transistor device includes a conductive mounting flange, a dielectric window substrate attached to the mounting flange. The window substrate has a perimeter surface and exposes a portion of the mounting flange. The RF power transistor device also includes an electrical terminal attached to the perimeter surface of the window substrate, a semiconductor die attached to the exposed portion of the mounting flange, the die having an electrode formed thereon, the electrode having an input terminal and an output terminal, a dielectric lid secured to the electrical terminal and substantially covering the semiconductor die, the lid carrying an electrical component, and fastening means for mechanically attaching the lid to the window and electrically coupling the electrode to the electrical component on the lid.
In accordance with a preferred method of conserving space on an RF power transistor package, the method includes providing a dielectric lid adapted to engage with an RF power transistor package, the dielectric lid comprising an electrical component mounted on an inside surface of the lid, providing a conductor extending from the electrical component such that the conductor will engage with a circuit on the power transistor package when the lid is engaged therewith, and providing means for mechanically securing the dielectric lid to the power transistor package.
As will be apparent to those skilled in the art, other and further aspects and advantages of the present invention will hereinafter appear.